Demystifying PCIe PIPE 5.1 SerDes Architecture

May 16

Artificial intelligence and machine learning are rapidly penetrating a wide spectrum of devices, driving the re-architecture of SoC designs and requiring more memory space and higher bandwidth to transfer and process data

Deepak Kumar Lnu

Deepak Kumar Lnu is a Principal Engineer at Synopsys, Inc. with over 16 years of experience in high-speed semiconductor design and verification. A recognized expert in PCI Express (PCIe) technology, he has contributed to multiple generations of the standard and played a key role in developing the industry’s first PCIe Gen6 and Gen7 Verification IPs. His name is officially included in the PCIe Base Specification, reflecting his contributions to the global computing infrastructure. Deepak is a Senior Member of IEEE and a fellow/member of several prestigious engineering bodies, committed to advancing Electronic Design Automation (EDA) and enabling innovation in AI, HPC, and cloud technologies.

Demystifying PCIe PIPE 5.1 SerDes Architecture

A Novel Approach to Speeding Up PCIe 6.0+ Designs - Compliance Load Board Verification